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* LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A, B, C to Y) = 18.5 ns typ (CL.
The HD74HCT138 has 3 binary select inputs (A, B, and C). If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables (G1, G2A and G2B) are provided to ease the c.
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